Commits · b403b9ec184e2231d387a34c4b8f03ebea458875 · Projects / White Rabbit Trigger Distribution

30 Jul, 2018 8 commits
- hdl: further fine-tuning of timing constraints · b403b9ec
  Dimitris Lampridis authored Jul 30, 2018
  
  b403b9ec
- sw:ut: do not compile it - not used · b94b6b8c
  Federico Vaga authored Jul 30, 2018
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  b94b6b8c
- sw:lib: add ARFLAGS into the Makefile · 832599e0
  Adam Wujek authored Jul 27, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  832599e0
- sw: add few .gitignore · a0315801
  Adam Wujek authored Jul 27, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
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  a0315801
- sw:tools: fix build rules · ad141db7
  Adam Wujek authored Jul 27, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  ad141db7
- sw: remove for loop from Makefile · baf92791
  Adam Wujek authored Jul 27, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  baf92791
- Merge branch 'proposed_master' into fvaga-proposed_master · 2894733f
  Federico Vaga authored Jul 30, 2018
```
This merges the software changes to make WRTd compile against Mock Turtle 4.0.
This needs also to point to a newer Mock Turtle commit.

During the merge I had to fix Makefile paths to mock-turtle since it has been
moved to the dependencies directory
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  2894733f
- dep: update mock-turtle · 7725e6a0
  Federico Vaga authored Jul 30, 2018
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  7725e6a0
27 Jul, 2018 15 commits
- hdl: further restructure and cleanup of dependencies and manifests · 9de10e18
  Dimitris Lampridis authored Jul 27, 2018
  
  9de10e18
- hdl: fix fetchto variable in Manifests · 8975076d
  Dimitris Lampridis authored Jul 27, 2018
  
  8975076d
- migrate all submodules to 'dependencies' folder at the root of the project · fc84eda0
  Dimitris Lampridis authored Jul 27, 2018
  
  fc84eda0
- remove double MT submodule · 3b46c921
  Dimitris Lampridis authored Jul 27, 2018
  
  3b46c921
- hdl: update timing constraints for svec/list_tdc_fd project · 895916a8
  Dimitris Lampridis authored Jul 27, 2018
  
  895916a8
- sw:fw: move rt to firmware · 0f1d42ea
  Federico Vaga authored Jul 23, 2018
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  0f1d42ea
- sw:rt: port to Mock Turtle 4.0 [UNTESTED] · d9f97688
  Federico Vaga authored Jul 23, 2018
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  d9f97688
- Merge branch adam-ci · eb448f2e
  Adam Wujek authored Jul 27, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  eb448f2e
- tests:firmware: add Makefile and .gitignore · ba051461
  Adam Wujek authored Jul 26, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  ba051461
- hdl:testbench: build rmq-udp firmware before running wrtd-system testbench · c495f412
  Adam Wujek authored Jul 26, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  c495f412
- tests:firmware:rmq-udp: move .config into configs/mt_defconfig · 0dff63f2
  Adam Wujek authored Jul 26, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  0dff63f2
- hdl:testbench: look also for a colon when greping output in Makefile · ae36bb3e
  Adam Wujek authored Jul 26, 2018
```
QuestaSim (at least version 10_5c), prints the summary after the
simulation like:
End time: 16:29:35 on Jul 26,2018, Elapsed time: 0:00:49
Errors: 1, Warnings: 9

However, the second line was recognized as a Warning and an Error.
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  ae36bb3e
- hdl:testbench: add Makefile for CI · f80bfe1a
  Adam Wujek authored Jul 24, 2018
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  f80bfe1a
- sw: reverse sender/receiver cpus in rmq_udp test used in wrtd-system testbench · 87e16c93
  Dimitris Lampridis authored Jul 27, 2018
  
  87e16c93
- hdl: fix assignment of RMQ to MT CPUs · ff70a363
  Dimitris Lampridis authored Jul 24, 2018
  
  ff70a363
24 Jul, 2018 1 commit
- hdl: bump urv core to bring in debug interface fix · 75ed93f4
  Dimitris Lampridis authored Jul 24, 2018
  
  75ed93f4
23 Jul, 2018 8 commits
- hdl/sim: update wrtd-system testbench to make use of rmq-udp test firmware · 3f5f59be
  Dimitris Lampridis authored Jul 23, 2018
  
  3f5f59be
- Add a simple test. · 84dd8b5b
  Tristan Gingold authored Jul 23, 2018
  
  84dd8b5b
- hdl/testbench: introduce wrtd-system testbench, work in progress · 0f641265
  Dimitris Lampridis authored Jul 23, 2018
  
  0f641265
- sw:tool: port to Mock Turtle 4.0 [UNTESTED] · 8ff80577
  Federico Vaga authored Jul 23, 2018
```
This is part of a more complex work. Here, I just fixed all the GCC errors
and warning. The next step will be to actually test it.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  8ff80577
- sw:lib: port to Mock Turtle 4.0 [UNTESTED] · f551c3ce
  Federico Vaga authored Jul 23, 2018
```
This is part of a more complex work. Here, I just fixed all the GCC errors
and warning. The next step will be to actually test it.
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  f551c3ce
- Add ether endpoint. · 09836380
  Tristan Gingold authored Jul 23, 2018
  
  09836380
- sw: fix building infrastructure · d1f9bff6
  Federico Vaga authored Jul 23, 2018
```
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  d1f9bff6
- Use direct instantiation of MT for svec. · 8d46f8a9
  Tristan Gingold authored Jul 23, 2018
  
  8d46f8a9
20 Jul, 2018 2 commits
- hdl: new top-level with latest WRPC and MT. Missing RMQ-EP · 4a68a12e
  Dimitris Lampridis authored Jul 20, 2018
  
  4a68a12e
- hdl: make it possible to synthesize list_tdc_fd with latest wr-cores and general-cores · 545983b7
  Dimitris Lampridis authored Jul 20, 2018
  
  545983b7
05 Jul, 2018 1 commit
- Create software directory and move sw content there. · fcdea67a
  Tristan Gingold authored Jul 05, 2018
  
  fcdea67a
04 Jul, 2018 2 commits
- connect endpoint. · 23fe4024
  Tristan Gingold authored Jul 04, 2018
  
  23fe4024
- list_tdc_fd: add mock turtle. · e6e1f0b2
  Tristan Gingold authored Jul 04, 2018
  
  e6e1f0b2
03 Jul, 2018 1 commit
- Adjust various parts so that the design can be analyzed. · 9652761d
  Tristan Gingold authored Jul 03, 2018
  
  9652761d
29 Jun, 2018 2 commits
- Add missing dependencies. · 1c2afd90
  Tristan Gingold authored Jun 29, 2018
  
  1c2afd90
- Minor changes to ensure hdlmake completion. · 35a0c4a9
  Tristan Gingold authored Jun 29, 2018
  
  35a0c4a9