In order to use the wired-OR logic of the
MLVDS standard, we need to output data only
when sending data.

If we are in output state we drive the data
pin to HI and use the direction pin as data,
so we can release the bus when not sending.

If we are in input state, we just use the data/
direction pins as usual.

This is safe to use with AFCv3 boards
and delivers fast boot times.

This file should be generated by hdlmake
tool every synthesis and not hardcoded as
it was before.

Now, all bitstreams are generated with:

 - SPI buswidth of 4
 - SPI fall edge = true
 - 3 MHZ SPI flash configuration
 - 32-bit support as we use 256Mb SPI flash

IOBUF primitives always have the "input"
signal available for further use. This means
that even when transmitting signals (buffer
is output) the input signal will have a copy
of the transmitted pulse.

This is principle is not a problem, but we
were using this signal to count received events,
so we changed this to use this signal only if
the buffer direction is set to input.

This is important as if the FMC1 does not
supply any clock we won't be able to send/
recv trigger events.

Also, it doesn't really matter to have
triggers with a local clk_sys clock,
as the triggers are treated as asynchronous
signal anyway.

The acquisition properties were inverted.

When using FMC250 @~250MHz, with 4 samples, 32-bits,
we don't have enough bandwidth to acquire all of this.

Instead, we just acquire exactly the amount
of bits this ADC provides and treat how to
split the data array in software.

This fixes #33 github issue.

This code was received by CAEN ELS under, relicensed
under MIT license.

AFCv3 doesn't work well with faster rates, like
50MHz. So, 12MHz should be OK.

dsp-cores added another generate statement, which chahge the
hierarchy of position_calc component. So, we change it here.

We can't include a prefix on registers
filling the whole 32-bits. Otherwise
wbgen generates MACROS for accessing
this field that generally results in
errors like:

error: left shift count >= width of type [-Werror]

Previously we were just assigning test
values to them. Now, they are actually
controlled by the fmcpico_1M.

These are just controlled by Wishbone.

These contraints are not correct for PBPM
as the CE for this board are 1 for TBT/FOFB
and 8 for MONIT/MONIT1.

This generic was recently added to the dsp-cores
repository.

This is for safety until we export these
signals to wishbone.

Using VHDL dor DDR core issues an error.
No idea when that happens, unless re-target
my project for Verilog and regenerate the DDR
core.

This is needed as dsp-cores changed
xwb_position_calc_core interface.