- 03 Nov, 2022 1 commit
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Tristan Gingold authored
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- 20 Oct, 2021 1 commit
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Tristan Gingold authored
Avoid multiple definition of the same unit. Avoid warnings from hdlmake.
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- 24 Jul, 2020 5 commits
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Dimitris Lampridis authored
2.0.0 - 2020-07-24 ================= https://www.ohwr.org/project/ddr3-sp6-core/tree/v2.0.0 Added ----- - Generics to control granularity of Wishbone ports - Option for active-high reset - Micron DD3 BFM - SystemVerilog testbench Changed ------- - Complete rewrite of the Wishbone interface to improve compatibility, performance and code readability Removed ------- - Unused file ``rtl/ddr3_ctrl_wb_single.vhd``
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
This is done in order to: 1. Fix incompatibilities with pipelined wishbone 2. Improve performance 3, Improve code readability
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- 10 Jan, 2020 1 commit
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Dimitris Lampridis authored
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- 20 Dec, 2019 1 commit
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Dimitris Lampridis authored
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- 25 Jul, 2019 6 commits
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 13 Dec, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
ddr3_ctrl_wb: no need to check for wb_cyc when checking for wb_stb_valid, the latter includes the former.
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- 23 Nov, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 26 Oct, 2018 1 commit
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Dimitris Lampridis authored
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- 19 May, 2016 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 24 Feb, 2016 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
hdlmake does not allow by default local variables in included Manifest.py files. So, when this core is included in a bigger project (such as FMC-ADC), it should not have any local variables in its local Manifest.py file. Tested with SPEC and SVEC versions of FMC-ADC, works.
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- 25 Jun, 2015 1 commit
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Javier D. Garcia-Lasheras authored
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- 17 Feb, 2015 1 commit
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Matthieu Cattin authored
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- 19 Jul, 2013 1 commit
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Matthieu Cattin authored
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- 28 Mar, 2013 1 commit
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Matthieu Cattin authored
Command strobe should asserted even if it is already 1.
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- 30 Nov, 2012 1 commit
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Matthieu Cattin authored
Was not porperly generating the command strobe to ddr interface in case of wishbone block transfers.
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- 19 Nov, 2012 1 commit
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Matthieu Cattin authored
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- 16 Nov, 2012 2 commits
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Matthieu Cattin authored
The command enable signal was not properly generated for single read cycle.
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Matthieu Cattin authored
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- 24 Oct, 2012 2 commits
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mcattin authored
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@110 739e5516-d4a2-47df-ba96-5610c1fa693f
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mcattin authored
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@109 739e5516-d4a2-47df-ba96-5610c1fa693f
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- 09 Aug, 2012 1 commit
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mcattin authored
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@108 739e5516-d4a2-47df-ba96-5610c1fa693f
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- 08 Aug, 2012 1 commit
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mcattin authored
Modify Manifests accordingly. git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@107 739e5516-d4a2-47df-ba96-5610c1fa693f
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- 16 Jul, 2012 1 commit
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mcattin authored
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@106 739e5516-d4a2-47df-ba96-5610c1fa693f
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- 11 Jul, 2012 3 commits
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mcattin authored
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@105 739e5516-d4a2-47df-ba96-5610c1fa693f
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mcattin authored
git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@104 739e5516-d4a2-47df-ba96-5610c1fa693f
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mcattin authored
This is to allow different configuration (FPGA/memory chip) for the same port. Add re-generated core with new names. git-svn-id: http://svn.ohwr.org/ddr3-sp6-core/trunk@103 739e5516-d4a2-47df-ba96-5610c1fa693f
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