Closed
Milestone
layout-v1.0
Unstarted Issues (open and unassigned)
0
Ongoing Issues (open and assigned)
0
Completed Issues (closed)
89
- [L14] X:124mm Y:30mm move SFP.MGT_Tx_P/N so that it lays fully over continuous GND in L13.
- [fpga-pl-mgts] SATA_TX vs SATAC_TX have P/N swapped!
- [L1] IC22, IC32 layout
- [L1] Switching current loops for IC31/IC30 are not small
- larger antipads on gnd and power planes
- some nets not connected to the centre of the VIA
- verify power polygons
- possible cross-talk between L7, L8?
- spacing between ESD strip 1 and 2 should be 20mm
- check if SFP inserted in the cate will not conflict with the front panel extraction handle
- [L14] X:199.75mm Y:25.825mm potentially unrouted net MGT2_RxC_P - consisting of 2 traces barely connected together
- stitch board outline with gnd vias wherever possible
- maximise decoupling capacitor track widths
- various board texts
- rework mechanical layers
- power plane pullback distance
- boot mode function table
- component designator position
- silkscreen font size
- silk to soldermask clearance set to 0
- press-fit tooling
- FMC mounting holes should be connected to chassis ground (not signal GND)
- GND track width for FMC connector
- add ground via under DDR chips
- "mouse bites" for PCB depanelization
- remove thermal relief for press-fit connectors
- power via hole size
- [L12] diff pair deskew
- stitch gnd top and bottom polygons next to DDR chips
- polygons on signal layer
- P1V8 power plane
- connect heat-sink mounting hole to GND
- create xsignals between DDR chips for command signal group
- polygon pour cutout beneat FPGA and FMC connector
- [BSilk] many components have their designators removed
- [L14] possible acid traps
- [L14] 3 ESD strips on the lower edge are not connected to anything
- [L14] check all MGT diff pairs routing to ensure they have smooth corners
- [L14] X:194mm Y:53mm: SLOT4.LVDS_8 diff pair with 2 sharp corners while later before vias it's smooth
- [L12] X:109mm Y:50mm MGT_CLKREF.CLK_P/N have sharp corners
- [multiple layers] Various traces widths used for same class slow signals
- [L7] some clock lines near IC4 are missing GND return vias (like it's done for 7_PE_CLK_P/N)
- [L5] X:116mm Y:39mm sharp corner on otherwise smooth-cornered transceiver lane
- [L5] X:217mm Y:50.5mm: what's the reason to have this via?
- [L3] X:193mm Y:45mm 7_SERVMOD_N track touches the via, but barely
- [L3] some FMC MGT lanes have 1 sharp edge in otherwise soft-edged routing
- [multiple layers] not enough stitching vias on some GND polygons
- [multiple layers] not needed polygon pour cutouts?
- [L1] X:187mm Y:43mm <n>_SERVMOD_N lines could be router nicer, with equal spacing
- [L1] SLOT2.LVDS_6_P/N - part of the diff pair has rounded corners, part has sharp corners
- [L1] X:130mm Y:9mm: is there a break between GND polygon and GND pads of IC41?
- [L1] not needed tracks cutting thermal reliefs
- [L1] possible acid traps
- [L1] what is the role of pads e.g. on WR_DAC lines (DIN, SYNC1, SYNC2, SCLK)?
- [L1] irregular (random?) traces thickness from FPGA pads
- [L1] ESD strip3 should include also mounting hole for the front panel
- [L1] add some more GND return vias for diff pairs crossing layers
- [General] what is the estimated cost of this board today excluding the FPGA price?
- [TSilk] CERN OHL license
- [TSilk] modifications
- [General] Do we ABSOLUTELY need 0201 capacitors and resistors?
- [L14] C43 not at 45 degree angle
- [L14] Could IC24 be placed on top side of PCB?
- [L6GND] small cutouts placed around certain pins of IC1 (like SRC_CLK_SEL_R) or P2V5 vias next to C297. What are they for?
- [L5] DDR4 PAR signal (FPGA pin AH18), minor plane crossing with L4PWR.
- [General] minor impedance discontinuities - on slow LVDS improve only if possible
- [General] check DDR4 rules
- [General] Length match FMC MGTs (difference of 10 mm)
- [General] Length match FMC.CLK_M2C 0 and 1 (difference of 20 mm)
- [sch] Power IC3 from VBus instead of 3v3.
- [L1] Check via count vs current on P5VREG near C296
- [General] try to equalize via counts from high current power supplies to power planes
- [L1, L14] IC30, IC31 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
- [L1, L14] IC1, IC4 - add more vias on the thermal pads and expose (no soldermask) GND area on bottom layer.
- [L1] C308/L12 and around: minor component courtyard overlaps. No real collision between components.
- [General] Clearance rule: do we really need 3 mils?
- [General] Reinforce mounting pads such as B3 with via rings.
- [General] Mounting pads for FPGA heatsink/fan
- [General] Clearance to unplated holes is a bit too tight
- [ General] Disable polygon connection (including thermals) to all BGA pads
- [General] (X:216mm Y:88.5mm) what's the purpose of that via between backplane P6 connector pins? There is GND pin right next to it.
- [General] Impedance of differential pairs not always 100 Ohm, very thin traces (0.075mm)
- [General] Clock lanes <n>_PE_CLK_P/N of backplane connector P5 (J31) shall be length matched to provide low-skew clock distribution
- slot7.lvds_0 and slot7.lvds_8 have p/n swapped comparing to FPGA pins functions
- Large vias copied from EDA-03828
- Swap FMC section with SFP section
- J6 could be closer to FPGA, it is there to power optional Zynq fan
- can we remove LD6 from the front panel and move MicroUSB (J2) to the front panel instead?
- [General] Xilinx BGA package delays