- 04 Mar, 2014 2 commits
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Matthieu Cattin authored
hdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).
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Matthieu Cattin authored
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- 17 Feb, 2014 1 commit
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Matthieu Cattin authored
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- 07 Feb, 2014 1 commit
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Matthieu Cattin authored
The new GN4124 core version implements a timeout and ERR treatment on the csr wishbone interface.
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- 30 Jan, 2014 1 commit
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Matthieu Cattin authored
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- 28 Jan, 2014 1 commit
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Matthieu Cattin authored
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- 17 Jan, 2014 5 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 16 Jan, 2014 3 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 09 Jan, 2014 1 commit
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Matthieu Cattin authored
-> memory map changed!
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- 07 Jan, 2014 4 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 06 Jan, 2014 1 commit
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Matthieu Cattin authored
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- 13 Dec, 2013 1 commit
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Matthieu Cattin authored
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- 06 Dec, 2013 1 commit
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Matthieu Cattin authored
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- 11 Nov, 2013 2 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 18 Sep, 2013 4 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 29 Jul, 2013 12 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
hdl: Fix ddr adr and data wb slave number, add carrier type generic, increment ddr address counter on cyc falling edge.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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