Was using custom coregen fifo and dpram.

Calibration data storage in eeprom with sdbfs (was ipmi only).

no_coregen branch generic_fifo is buggy, not outputing the last written data
from time to time.
Was causing the gennum core to hang (waiting forever on the last data).

Tying to find the PC hang bug.

This was missing modification from the svn local copy...

Was using the external reset (from gn4124 chip) only.
Now it uses the system reset taking into account the external reset
and the system clockpll lock status.

Update Manifest to take the git versions of the ddr and gn4124 cores.

Because a migration to git is foreseen.


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@132 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Added the *play* project, as a reference project to the hdlmake tutorial, as well as an exampleof accessing SPEC registers via the *rawrabbit* driver.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@131 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@130 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@129 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Move drawings to figures folder.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@128 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Add more details on data format.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@127 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Wishbone components map updated to fit the new entities.
 -> generic to select interface mode (classic/pipelined) and address granularity (byte/word).
 -> wishbone address port size.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@126 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

New generated core naming.


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@125 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@124 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Now the interrupt is generated when the DDR interface write FIFO is empty.
This is to avoid read request from the host before all data are written to the DDR memory.

Add synthesis, p&r and timing reports.
Remove generated simulation files from repo.



git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@123 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@122 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@121 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@120 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@118 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@117 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4