The following changes were done:

1. Point all submodules to new OHWR

2. update ddr3-sp6-core to latest master because the previous commit
(8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test!

3. remove etherbone-core

4. update general-cores to latest master and use the updated gc_ds182x_readout module

fmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line programmable from the host to adjust the timing. Possible fix for the 131us bug

hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead

rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing

rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing

From Tom's dma branch.