compiled from commit:
a9add108 Merge branch 'adam-lldp-rebased' into proposed_master

Compiled from wrpc-sw commit:
c0e116b: simpler sdbfs creation by using parameters provided by Syscon HDL module

The streamer has a new start-up delay counter. this delay needs to be
shorter for simulation. the fact that we are running simulation was not
passed to the Tx streamer, now it is passed.

by default, the bram content for synthesis is specified. it is only
overriden by simulation. In this way, if the top can be both, simulated
and synthesized.

The binary did not work. I do not know why. I just recompiled wrpc-sw
with wrpc_sim_defconfig configuration and it works.

compiled from commit:
25f814a3 update ppsi to fix 1-pps generation in Master mode

PPS csync is asserted one 125MHz ref clock cycle before the actual PPS. It can be used for aligning another signal to the PPS.

platform/xilinx: add generics to Xilinx platform to select which GTP channel to use (defaults to ch1)