- 27 Aug, 2014 2 commits
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Lucas Russo authored
In order to program the FPGA via JTAG in the AFCs is necessary to first configure the SCANSTA chip as a transparent bridge.
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Lucas Russo authored
The sync chains module was just a sync FIFO for synchronizing all data chanins to a single clock domain. however, this synchronization is already done, as all channels are clock-crossed to the same reference clock.
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- 22 Jul, 2014 1 commit
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Lucas Russo authored
This will ease timing on the datapath, as we have registered the MUX output before the next components.
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- 15 Jul, 2014 3 commits
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Lucas Russo authored
Add Xilinx MAX_FANOUT attribute to try to reduce the reset fanout
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Lucas Russo authored
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Lucas Russo authored
As the design gets bigger, it may be difficult to meet timing constraints for all Wishbone paths, specially with nested crossbars. This patch adds a generic option to enable an additional regsiter on the Wishbone path to ease timing.
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- 11 Jul, 2014 1 commit
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Lucas Russo authored
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- 07 Jul, 2014 3 commits
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Lucas Russo authored
The previous default value was "VARIABLE", which has the advantage of enabling intiial delay values in the UCF. However, changing the value dynamically (in software) is not much pratical as we would need to update the tap value one by one, incrementally. The current value "VAR_LOADBLE" does not accept the initial delay value in the UCF, but changing them in software is easier.
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Lucas Russo authored
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Lucas Russo authored
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- 26 Jun, 2014 2 commits
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Lucas Russo authored
This allows the selection of the idelayctrl primitive through the module top level
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Lucas Russo authored
Now, it is possible to select an instance of idelayctrl primitive or not. This is particularly useful when synthesizing a large design that involves other idelayctrl primitives beyond our control, such as Xilinx DDR controllers
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- 19 Jun, 2014 9 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
In the new version of hdlmake, we need to supply the ISE version we want to use
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Lucas Russo authored
This was not supposed to be here, but we include it here, as to not loose the changes
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
If we let the synthesis tool in its defauts attributes, the pipeline gets removed and moved into a SRL primitive, causing PCBs having ADC FMC data lines routed to oppositte FPGA I/O banks to not meet timing. With these attributes we intruct XST and MAP to keep the pipeline and not suck them into an SRL, which would hurt the ability by MAP and PAR to move the pipeline registers around to meet timing.
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Lucas Russo authored
For single-ended pins, we can't use LVDS standard, so we default to LVCMOS25. If the standard is actually different from this, we could still override it in the UCF file
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Lucas Russo authored
Thse were causing lgic contention with some specific Xilinx XST options, particularly KEEP_HIERARCHY = SOFT, to keep the hierarchy so we could properly apply some AREA constraints. The tool would GND these NETS anyway.
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- 02 Jun, 2014 3 commits
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Lucas Russo authored
In the 7-SERIES families, the PLL and MMCM are two separate primitives, very similar to each other. In other to reduce the number of MMCM usage, we changed it to PLL here
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Lucas Russo authored
This constraint was causing conflicts with the other ones and a wrong PLL PERIOD contraint was taken into account
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Lucas Russo authored
This allow us to select a broader range of frequencies, in order to generate a 100 MHz clock from a 125 MHz clock source, for instance
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- 14 May, 2014 2 commits
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Lucas Russo authored
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Lucas Russo authored
Warning: MAP and PAR can take a long time due to poor placement of the GTP tranceiver for the PCIe core
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- 10 May, 2014 4 commits
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Lucas Russo authored
On 7-SERIES FPGAs, we need to explicitily instantiate a BUFMR primitive in order to use a MRCC pin as a drive to a Multi-Region BUFR or BUFIO. Now, we can select which ones of used clocks are LOCed to MRCC pins and which ones are not.
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Lucas Russo authored
For single-ended inputs, it is necessary to use A single-ended standard, obviously
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Lucas Russo authored
Exposed the idelay type desired to user. This brings flexibility on selecting the different delay types for different FPGA devices
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Lucas Russo authored
For 7SERIES FPGAs, the iodelay primitive has beed updated to idelaye2. So, we add a differente generate for these FPGAs
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- 09 May, 2014 2 commits
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Lucas Russo authored
The xwb_ethmac_adapter component uses compoenents from the Etherbone core. As its naming has changed a while ago, we need to update the components interfaces here
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Lucas Russo authored
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- 06 May, 2014 6 commits
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Lucas Russo authored
The g_ref_clk is out of bounds when using external clock reference. So, we must use the f_adc_ref_clk () function
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Lucas Russo authored
Replace direct usage of ref_clk generic by the f_adc_ref_clk () function, which correctly selects the adc ref clk in all cases, even when using an external reference
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Lucas Russo authored
As the ref_clk equal to "c_num_adc_channels" means "external reference clock" we use a function to generate the correct reference clock in all cases
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Lucas Russo authored
The interface for the FMC ADC module have changed, so we update them here in the top files
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Lucas Russo authored
As the previous commit changed the interface of the ADC module, we update them here
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Lucas Russo authored
Add option to use an external supplied clock (usually from another PLL or global clock buffer inside the FPGA) to clock the data to downstream FPGA logic. This implies the ASYNC FIFO after the first ADC acquisition and the synchronization betweem multiple ADC channels. This is useful when instantiating more than one ADC module, as we don't need two reference clocks and more than one reference would only make things harder.
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- 30 Apr, 2014 2 commits
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Lucas Russo authored
The xwb_acq_core had a wrong addressing granularity. The correct one is BYTE
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Lucas Russo authored
Replaced hardcoded constant values to the ones available in the bpm core constant packages
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