Updated with submodule FIDSIP that ORs the CMPin and extenedcmpin in hardware. This avoids problems with signals that are longer than the extended signal

Zynq PS core and .xdc constraints modified for fasec V2; wb_i2c_master_2 added for mdio pullups - don't use in software

update of axi_wb_i2c_master modules because of tricell errors resulting in broken i2c; still to be done for wrc

fasec_hwtest module bugfix; set_registers tcl script changed because of out of context IPs; after synthesis

fasec_hwtest and wrc_1p_kintex7 modules updated for WR debugging and FMC hardware tests with PS interrupts

design uses submodules only (instead of HDD repo); wrpc links some debug clocks to fasec_hwmodule for debugging

after reimportation, synthesis and implementation OK; still work needed on timing constraints though