- 12 Oct, 2017 1 commit
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Pieter Van Trappen authored
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- 11 Oct, 2017 4 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
update of axi_wb_i2c_master modules because of tricell errors resulting in broken i2c; still to be done for wrc
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- 21 Jun, 2017 2 commits
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Pieter Van Trappen authored
fasec_hwtest module bugfix; set_registers tcl script changed because of out of context IPs; after synthesis
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Pieter Van Trappen authored
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- 20 Jun, 2017 1 commit
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Pieter Van Trappen authored
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- 31 May, 2017 1 commit
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Pieter Van Trappen authored
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- 24 May, 2017 2 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 15 May, 2017 2 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 12 May, 2017 2 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 11 May, 2017 5 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 13 Apr, 2017 3 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 12 Apr, 2017 1 commit
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Pieter Van Trappen authored
fasec_hwtest and wrc_1p_kintex7 modules updated for WR debugging and FMC hardware tests with PS interrupts
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- 27 Mar, 2017 3 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
design uses submodules only (instead of HDD repo); wrpc links some debug clocks to fasec_hwmodule for debugging
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Pieter Van Trappen authored
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- 23 Mar, 2017 1 commit
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Pieter Van Trappen authored
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- 22 Mar, 2017 2 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 21 Mar, 2017 2 commits
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Pieter Van Trappen authored
after reimportation, synthesis and implementation OK; still work needed on timing constraints though
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Pieter Van Trappen authored
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- 16 Mar, 2017 4 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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- 15 Mar, 2017 1 commit
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Pieter Van Trappen authored
design goes succesfully through synthesis and implementation; timing constraints not met caused by clk_fpga_1 - ext. 10 MHz - which should not cause problems
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- 14 Mar, 2017 3 commits
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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Pieter Van Trappen authored
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