Commits · 010020ed8a33b8e1898a92afa2297d68d2abe6ce · Projects / FMC ADC 100M 14b 4cha - Gateware · Open Hardware Repository

17 Jan, 2014 2 commits
- doc: Updating documentation for release v3.0 (in progress). · 010020ed
  Matthieu Cattin authored Jan 17, 2014
  
  010020ed
- syn: svec-fmc-adc firmware release 3.0 · 92c891b4
  Matthieu Cattin authored Jan 17, 2014
  
  92c891b4
16 Jan, 2014 3 commits
- hdl: Make mezzanine reset inactive by default on the svec. · d6208778
  Matthieu Cattin authored Jan 16, 2014
  
  d6208778
- syn: spec-fmc-adc firmware release 3.0 · f48f3593
  Matthieu Cattin authored Jan 16, 2014
  
  f48f3593
- hdl: Make mezzanine reset inactive by default on the spec. · 3c4e2201
  Matthieu Cattin authored Jan 16, 2014
  
  3c4e2201
09 Jan, 2014 1 commit
- hdl: Move fmc eic and timetag core to mezzanine (behind the wb bridge). · b536d7b4
  Matthieu Cattin authored Jan 09, 2014
```
-> memory map changed!
```
  b536d7b4
07 Jan, 2014 4 commits
- hdl: Update fmc adc eic sdb records (with same data as in spec version). · f0c9a78a
  Matthieu Cattin authored Jan 07, 2014
  
  f0c9a78a
- hdl: Add non-null meta field for timetags (mainly for test). · d3c248bc
  Matthieu Cattin authored Jan 07, 2014
  
  d3c248bc
- hdl: Change trigger position register to byte-address (was sample-address). · 5c6c0ed7
  Matthieu Cattin authored Jan 07, 2014
  
  5c6c0ed7
- hdl, doc: Delete irq controller files (not used any more). · ddf254ee
  Matthieu Cattin authored Jan 07, 2014
  
  ddf254ee
06 Jan, 2014 1 commit
- hdl, doc, sim: Fix sdb bridge offset address, add config ok flag, update doc in progress. · 0580effb
  Matthieu Cattin authored Dec 20, 2013
  
  0580effb
13 Dec, 2013 1 commit
- hdl: Insert trigger time-tag in data, after post-trigger samples. · b48832a9
  Matthieu Cattin authored Dec 13, 2013
  
  b48832a9
06 Dec, 2013 1 commit
- hdl: Change interrupt scheme, now uses eic + vic. Changes in memory map. · 94774b66
  Matthieu Cattin authored Dec 06, 2013
  
  94774b66
11 Nov, 2013 2 commits
- doc: Update todo list. · a7b6eaf5
  Matthieu Cattin authored Nov 11, 2013
  
  a7b6eaf5
- hdl: Update vme core to latest version. · e513c580
  Matthieu Cattin authored Nov 11, 2013
  
  e513c580
18 Sep, 2013 4 commits
- hdl: Adapt xwb_clock_crossing generic to general-cores proposed master branch. · 10d68343
  Matthieu Cattin authored Sep 18, 2013
  
  10d68343
- hdl: Fix "unused" field width of the reset register. · 2f858137
  Matthieu Cattin authored Aug 15, 2013
  
  2f858137
- hdl: Increase decimation register width from 16 to 32 bits. · f9628bce
  Matthieu Cattin authored Aug 08, 2013
  
  f9628bce
- hdl: Uses general-cores proposed_master branch, since generic fifo have been fixed. · 4ace9221
  Matthieu Cattin authored Aug 07, 2013
  
  4ace9221
29 Jul, 2013 13 commits
- syn: Svec firmware release 1.0 · df8d5123
  Matthieu Cattin authored Jul 29, 2013
  
  df8d5123
- hdl: Add a software reset register to reset the mezzanines related cores. · d742c0b8
  Matthieu Cattin authored Jul 29, 2013
  
  d742c0b8
- hdl: Update wbgen2 and re-generate cores. · 2565e724
  Matthieu Cattin authored Jul 23, 2013
  
  2565e724
- hdl: svec ise project for new interrupt controller. · 414ece4f
  Matthieu Cattin authored Jul 23, 2013
  
  414ece4f
- sim: Add random data acquisition to simulation to test interrupts. · 2756acdd
  Matthieu Cattin authored Jul 23, 2013
  
  2756acdd
- hdl: Fix comment in sdb meta infor package. · aa40d03f
  Matthieu Cattin authored Jul 23, 2013
  
  aa40d03f
- hdl: Change interrupt controller for the wbgen2 one (level output). · a1755df7
  Matthieu Cattin authored Jul 23, 2013
  
  a1755df7
- sim: Add svec simulation files. · 7f9b4cef
  Matthieu Cattin authored Jul 19, 2013
  
  7f9b4cef
- hdl: Fix ddr adr and data wb slave number, add carrier type generic, increment… · 3f5a3b23
  Matthieu Cattin authored Jul 19, 2013
```
hdl: Fix ddr adr and data wb slave number, add carrier type generic, increment ddr address counter on cyc falling edge.
```
  3f5a3b23
- hdl: Add svec design files. · 7f782cc2
  Matthieu Cattin authored Jul 17, 2013
  
  7f782cc2
- syn: Spec firmware release 2.0 · 13354443
  Matthieu Cattin authored Jul 29, 2013
  
  13354443
- git: Add .bin and .bit to gitignore file. · e8ce11fd
  Matthieu Cattin authored Jul 29, 2013
  
  e8ce11fd
- hdl: Fix software reset field name (add _n for active low signal). · a7445ce9
  Matthieu Cattin authored Jul 29, 2013
  
  a7445ce9
26 Jul, 2013 2 commits
- doc: Replace spec by carrier to be more generic. · 063fb87d
  Matthieu Cattin authored Jul 26, 2013
  
  063fb87d
- hdl: Add a software reset register to reset the mezzanine related cores. · 08c8d3ae
  Matthieu Cattin authored Jul 26, 2013
  
  08c8d3ae
25 Jul, 2013 1 commit
- hdl: Update wbgen2 and re-generate. Move .tex file to a carrier specific dir. · ee8954d0
  Matthieu Cattin authored Jul 25, 2013
  
  ee8954d0
23 Jul, 2013 5 commits
- syn: Updated wbgen2 cores, new serdes clock pll feedback scheme, new memory… · b1332226
  Matthieu Cattin authored Jul 23, 2013
```
syn: Updated wbgen2 cores, new serdes clock pll feedback scheme, new memory mapping, new version of the ddr3 interface.
```
  b1332226
- doc: Update memory map and figures. · 8bfeff03
  Matthieu Cattin authored Jul 23, 2013
  
  8bfeff03
- hdl: Update wbgen2 and re-generate cores. · f61a80f5
  Matthieu Cattin authored Jul 23, 2013
  
  f61a80f5
- doc: Add firmware architecture diagram for svec version, update the spec one. · 5f189f2c
  Matthieu Cattin authored Jul 23, 2013
  
  5f189f2c
- git: Update .gitignore file. · b76b7cba
  Matthieu Cattin authored Jul 23, 2013
  
  b76b7cba