- 11 Mar, 2013 5 commits
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Matthieu Cattin authored
This information is now in sdb header (meta info).
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Matthieu Cattin authored
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Matthieu Cattin authored
SPEC front panel leds reserved for WR. SPEC aux leds used as follow: 0 = fpga programmed (heartbeat) 1 = trigger 2 = acquisition done 3 = dma done
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Matthieu Cattin authored
Was using the wrong fifo empty signal to generate the valid signal.
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Matthieu Cattin authored
Is not recording the rigth amount of samples in the ddr.
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- 08 Mar, 2013 2 commits
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Matthieu Cattin authored
Was using custom coregen fifo and dpram.
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Matthieu Cattin authored
Calibration data storage in eeprom with sdbfs (was ipmi only).
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- 07 Mar, 2013 7 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 05 Mar, 2013 5 commits
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Matthieu Cattin authored
no_coregen branch generic_fifo is buggy, not outputing the last written data from time to time. Was causing the gennum core to hang (waiting forever on the last data).
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 21 Feb, 2013 1 commit
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Matthieu Cattin authored
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- 25 Jan, 2013 1 commit
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Matthieu Cattin authored
Tying to find the PC hang bug.
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- 30 Nov, 2012 8 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
This was missing modification from the svn local copy...
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
Was using the external reset (from gn4124 chip) only. Now it uses the system reset taking into account the external reset and the system clockpll lock status.
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Matthieu Cattin authored
Update Manifest to take the git versions of the ddr and gn4124 cores.
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- 19 Nov, 2012 1 commit
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Matthieu Cattin authored
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- 14 Nov, 2012 1 commit
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mcattin authored
Because a migration to git is foreseen. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@132 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 15 Oct, 2012 1 commit
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tstana authored
Added the *play* project, as a reference project to the hdlmake tutorial, as well as an exampleof accessing SPEC registers via the *rawrabbit* driver. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@131 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 02 Oct, 2012 1 commit
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mcattin authored
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@130 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 30 Aug, 2012 1 commit
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mcattin authored
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@129 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 29 Aug, 2012 1 commit
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mcattin authored
Move drawings to figures folder. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@128 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 16 Aug, 2012 1 commit
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mcattin authored
Add more details on data format. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@127 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 06 Aug, 2012 1 commit
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mcattin authored
Wishbone components map updated to fit the new entities. -> generic to select interface mode (classic/pipelined) and address granularity (byte/word). -> wishbone address port size. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@126 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 11 Jul, 2012 2 commits
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mcattin authored
New generated core naming. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@125 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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mcattin authored
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@124 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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- 09 Jul, 2012 1 commit
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mcattin authored
Now the interrupt is generated when the DDR interface write FIFO is empty. This is to avoid read request from the host before all data are written to the DDR memory. Add synthesis, p&r and timing reports. Remove generated simulation files from repo. git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@123 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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