Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

hdl: stop using local ext_pulse_sync, switch to general-cores sync chain for external trigger as well

hdl: replace custom ext_pulse_sync with general-cores module for time trigger sync, cleanup timetag_core, tested on SPEC in the lab, works

Also point to new, stable release of DDR3 core (1.0) which also fixes the reset logic

It is more natural to read a zero value from a register during normal operation / after reset. Also avoids the extra logic outside of the wbgen carrier_csr which was needed to accomodate the non-default value of '1'

hdl: prevent FSM from going through the pre-trigger state, if there are no pre-trigger samples to be acquired. Fixes the error in the samples counter register when pre_trigger samples was zero.

Because of a -yet to be fully understood- bug, acquisition produces
corrupted samples when number_of_samples is exactly equal to multi_shot dpram
size. So for now, number_of_samples should be less than multi_shot ram size.

hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results