- added 2 out HMQs
- changed cpu_mem_sizes
- added crossbar that gives access to both CPUs to the fmc_masterfip_core
- added logic for the fd_wdgn and fd_txerr handling
- relevant changes on fmc_masterfip_csr.wb regs

- changes on fmc_masterfip_csr.wb regs
- increased out hmq to 6
- different cpu_mem_sizes between CPU0 and CPU1
- general cleanup

- general code cleanup

-fmc_masterfip_csr.vhd: macrocyc, turnar and silen counters are 31bits not 32

- added fd_txena signal to WRNC csr
- cleanup

-updated masterfip core: up to 263 frame bytes, corrected core reset, added ext_sync and adc supply signals, ucf.
-updated testbench

small changes on signals names of fmc_masterfip_csr

also small correction on the rx_regs

new architecture of masterfip; only the ser/des in vhdl and then the WRNC will do all the logic; in this commit there is no WRNC, it is a test design for the ser/des.