PoR input pin added 

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@109 7f0067c9-7624-46c7-bd39-3fb5400c0213

wf_prod_permit and wf_cons_outcome units added.

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wf_tx: renamed to wf_tx_serializer
wf_deglitcher: renamed to wf_rx_deglitcher
wf_cons_bytes_from_rx: renamed to wf_cons_bytes_processor
wf_slone_bytes_to_DATO renamed to: wf_bytes_to_dato
wf_prod_bytes_to_tx renamed to: wf_prod_bytes_retriever
wf_slone_prod_DATI_bytes_sampler renamed to wf_prod_bytes_to_dati
new nanoFIP outputs added: u_cacer, u_pacer, r_tler, r_fcser; fx_rxd, fx_rxa, fx_txd renamed to fd_rxd, fd_rxcdn, fd_txd; pdc file updated as well.
no broadcast vars in slone mode finally!
broadcast var 91h instead of 04h.
wf_crc: timing for checking the crc bytes changed (before there was no check with respect to the FES)
wf_engine_control: removed the check of # bytes in slone mode; if > 2 data bytes arrive, nanoFIP puts to DATO the first 2.
new units wf_production and wf_consumption created to clearify the structure!


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removal from wf_engine_control of the check of rp_dat length in slone (there may be > 2 data bytes)

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@99 7f0067c9-7624-46c7-bd39-3fb5400c0213

changes on treatment of reset variable
temp alternative file for wf_reset_unit that assumes a PoR input
small changes regarding reseting the rx_tx_osc unit 

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in memory mode, sampling of DAT_I takes place when output ACK_I is active (before was 2 DAT_I before).
all signals buffered 3 times.
tx_state machine from Mealy to Moore

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wf_rx and wf_engine_control state machines changes from mealy to moore

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@74 7f0067c9-7624-46c7-bd39-3fb5400c0213

(consumed vars: PDU_TYPE and Length bytes received, 
produced vars: VAR3_ACC enabled only if ctrl, PDU_TYPE, Length and CRC bytes are correct;
sampling of dat_i takes place on the 1st clk tick after VAR3_ACC deasserted)

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@73 7f0067c9-7624-46c7-bd39-3fb5400c0213

- correction on bytes counters (there were errors when 124 data bytes had to be sent and the vectors of (6 downto 0) were changed to (7 downto 0))

 - correction on nFIP status byte generation

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changes also in reset_logic, after first testing with test bench asking for a produced var.

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Arch name in  in dpblockram_clka_rd_clkb_wr.vhd corrected

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@28 7f0067c9-7624-46c7-bd39-3fb5400c0213

modelsim and libero scripts added in hdl/cad

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@23 7f0067c9-7624-46c7-bd39-3fb5400c0213

Libero project created. 
Modelsim simulation script created. 

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Some details to fix, such as field drive special pins and reset width
Not simulated!

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