- 19 May, 2020 3 commits
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Pascal Bos authored
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Pascal Bos authored
updated pcie
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- 14 May, 2020 1 commit
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Peter Jansweijer authored
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- 12 May, 2020 3 commits
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Pascal Bos authored
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Pascal Bos authored
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Pascal Bos authored
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- 08 May, 2020 1 commit
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Peter Jansweijer authored
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- 07 May, 2020 2 commits
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Pascal Bos authored
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Pascal Bos authored
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- 29 Apr, 2020 1 commit
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Pascal Bos authored
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- 14 Apr, 2020 1 commit
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Pascal Bos authored
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- 03 Apr, 2020 1 commit
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Peter Jansweijer authored
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- 01 Apr, 2020 1 commit
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Pascal Bos authored
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- 27 Mar, 2020 4 commits
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Pascal Bos authored
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Pascal Bos authored
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Pascal Bos authored
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Pascal Bos authored
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- 24 Feb, 2020 1 commit
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Pascal Bos authored
changed pci_rst_n to perst_n, linked to wrc.bin linked to wrc.bin linked to wrc.bin corrected .bram file corrected .bram file corrected .bram file moved axi related files to general-cores (branch: pascal-axi) Fixed some bugs updated general cores with right manifest Updated tcl, added wrapper
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- 07 Feb, 2020 1 commit
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Pascal Bos authored
changed pci_rst_n to perst_n, linked to wrc.bin linked to wrc.bin linked to wrc.bin corrected .bram file corrected .bram file corrected .bram file
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- 30 Jan, 2020 10 commits
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Peter Jansweijer authored
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Peter Jansweijer authored
WRITE design clk_10m_p/n_i input is ibufds plus add XDC property for non-clock capable pins.
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Peter Jansweijer authored
Adding pll_wr_mode[1:0] for SPEC7 V2
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Peter Jansweijer authored
added BMM_INFO_DESIGN property to XDC
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Peter Jansweijer authored
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Peter Jansweijer authored
Add prsnt_m2c_l_i input pin. Prevents prsnt_m2c_l line to be influenced by a non driven FPGA pin after configuration done. (it did break the JTAG chain after configuration.
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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Peter Jansweijer authored
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- 28 Jan, 2020 5 commits
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Grzegorz Daniluk authored
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Pascal Bos authored
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Peter Jansweijer authored
upgrade clbv3_ref_design to VIVADO clbv3_ref_design: add valid xdc and bmm file; use generic g_direct_dmtd
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Peter Jansweijer authored
add wrpc/wrc_phy16_direct_dmtd.bram (spll KP parameters times 5 due to VCXOs range 20 ppm, incremented mode master lock timeout) wrc_phy16_direct_dmtd.bram build with: wrpc-sw.git peter_direct_dmtd SHA 50f1c0e ppsi.git peter_direct_dmtd SHA bf5f6de
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Peter Jansweijer authored
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- 20 Jan, 2020 1 commit
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Tomasz Wlostowski authored
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- 17 Dec, 2019 4 commits
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Grzegorz Daniluk authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
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Miguel Jimenez Lopez authored
- Add generic parameter for the SDB info of the auxiliary interface of the WRPC. - Export pps_csync and pps_valid ports from the WRPC.
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