PTS for WRS-LJ which is normal WRS with external AD9516 for 10MHz input.

    Change compile strategy.

   Previous mattia's lowjitter board use the second ext clock, but in current
WRSFL we can merge this ext clock to the normal ext clk.
   We could select the clk_ext_mul from the internal FPGA PLL (normal) or from
the external AD9516(low jitter).

https://github.com/AmeerAbdelhadi/Switched-Multiported-RAM
Commit 2a460ed

This saves some resources (memory in the switching core) as we no longer forward
frames to the endpoints that have no fiber connected.