Now, both designs use the generic
dbe_bpm_gen top design.

This is used by both FMC130 and
FMC250 top designs by modifying the
generic.

The previous DDR depth was hardcoded as 30,
which is right for kc705 board, but not for
AFC.

This fixes that by using the ipcores_pkg
definitions which are respective to the
DDR definitions of the used board.

This should help github issue #45,
but in my tests it didn't solve it
just yet. Nonethless, this was wrong
anyway.

This signal was being used as input into a Wishbone
register, as as a loopback to top design (so one
can probe this signal, if desired). However, on
refactoring the active_clk module, the loopback
signal fmc_pll_status_o was being driven by 2
nets: the loopback in the outer FMC module,
the internal loopback inside the active_clk
module.

This made the synthesis tool confused and
optimized away the Wishbone register signal.

This fixes #66 github issue.

Previously, on some cases, this signal was not being
calculated correcly and had the same value as the maximum
counting.

This fixes #65 github issue.

This will be used to select each ADC lines
will be updated with the current delay value.
This feature is already available on FMC130M_4CH.

This is already in general-cores repository.
So, we can't have it here.

This fixes #64 github issue.

Recent general-cores update (commit c422896e)
changed the xwb_i2c_master API, turning the module
into a multi-master one. With this, simple modifications
had to be made in modules using it.

With this, simulation works as expected
without manual intervention each time we
want to simulate the design

This makes it easier to generate the
FPGA bitstream, as only a single command
does everything needed.

This is already called by the generated
makefile. So, we don't need to call it twice.

This will allow for automatic generation of
synthesis_descriptor_pkg.vhd file on
synthesis-time.

Now, all one nedds to do is run "hdlmake"
and then "make"

Re-order each matching element to make it easier to update both scripts when needed.