- Synthesizable. Simulations reveals some little bugs in SPI cs_n pin and no loading of the registers.
- The VHDL syntax uses extensively type record entities, translation functions between IOs and records, attributes for defined type records...
- m25p32_core.vhd has now a package for itself m25p32_core_pkg.vhd. This file contains procedures for all the chain of spi instruction to write and read from the memory through SPI. It needs to add more cases.

It still needs work to do.

- Added documentation in pdf about register and memory map.
- Added testbench of the spi_master_core.

- Creation of a "hdl/ctdah_pkg: which share common components used along the design.
- Creation of m24p32 HDL core for managing access to m25p32 memory.
--- m24p32 is better structured by using packages, records and fucntions for easy translation.
- Creation of "hdl/spi_master_multified" for communicating with m24p32
- Modification "hdl/i2c_slave_wb_master" for better readability.

WR core implementation for CONV-TTL-BLO. Bitstream has been generated. Pending the test of WR upon a set up of a WR link.

Now is easy to understand all the FSMs and easy to debug, whenever it will be needed.
TODO:
- Fix a bug with regards a master wishbone operation at the end of a i2c slave write into sda operation

Possible small incompatibilities of independent HDL cores with its own testbench.
image1 status:
- i2c_slave is correctly initializated
- control is being heavily debugged
- triggers are being configured for proper use after initialization
TODO
- Check trigger initialization
- Complete i2c configuration check
- multiboot core to be checked

- Before read/write bit in ICAP_SPARTAN6 was inverted(solved)
- Missed a few states(dummies and so on) for correcty timing.
- TODO: MODE register should be added in the setting up. First the module should be tested in FPGA.

- Now is much more simplistic and better targeted for the client
- Draft: more functionality, board pictures and installation

UserGuide is confusing for driver's people. It is better suited as a complete HDL description of the CONV-TTL-BLO, hence it is moved as a different document.

Updating structure in core and regs. Added multicore_core_tb for checking internal fsm in multiboot_core.vhd

- logs are generated
- ICAP_SPARTAN6 needs 1u for correct startup
- Added flags for issuing GENERALx synchronization (TODO)
- Needs workaround multiboot_top_tb.vhd

UserGuide now includes the following modules:
- control
- trigger
- i2c slave
- multiboot

- General HDL specifications
- Complete description of the modules
-- i2c_slave_wb
-- trigger
-- multiboot