added all the submodules needed in ip_cores so that they are not taken from ip_cores/wr-node-core/hdl/ip-cores

direct access to the host is now given through the fmc0_host port of MT.

- cleaned up simulation

- general clean-up
- updated and renamed wbgen2 fileset.xml

- now providing to MT the current number of words rather than of bytes (rx_words_indx rather than rx_byte_indx)
- updated simulations

- added DAC SPI for the 25MHz OSC1 of the SPEC (mainly to be able to set it to the middle range where the OSC stability is maximum)
- added corresponding reg in fmc_masterfip_csr.wb
- cleanup of testbench

- added 2 out HMQs
- changed cpu_mem_sizes
- added crossbar that gives access to both CPUs to the fmc_masterfip_core
- added logic for the fd_wdgn and fd_txerr handling
- relevant changes on fmc_masterfip_csr.wb regs

- changes on fmc_masterfip_csr.wb regs
- increased out hmq to 6
- different cpu_mem_sizes between CPU0 and CPU1
- general cleanup

- general code cleanup

-fmc_masterfip_csr.vhd: macrocyc, turnar and silen counters are 31bits not 32