Commits · ab7d69d11dfdfd10f5bc79dee757ea5afa3f475e · Projects / White Rabbit core collection

11 Sep, 2012 1 commit
- Add prototype timing cores to the project Manifest so that hdlmake can see them. · ab7d69d1
  Wesley W. Terpstra authored Sep 11, 2012
  
  ab7d69d1
10 Sep, 2012 1 commit
- Merge branch 'gsi' · c1e6807b
  Wesley W. Terpstra authored Sep 10, 2012
```
Conflicts:
	modules/wr_endpoint/ep_clock_alignment_fifo.vhd
```
  c1e6807b
03 Sep, 2012 2 commits
- top/spec_1_1/wr_core_demo: improved host- and host-less carrier reset, removed obsolete files · 87bdf89b
  Tomasz Wlostowski authored Aug 20, 2012
```
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  87bdf89b
- spec_top: follow the changes in wr_gtp_phy_spartan6 module · 20851203
  Grzegorz Daniluk authored Sep 03, 2012
  
  20851203
30 Aug, 2012 1 commit
- wr_endpoint: packet filter decision queueing (fixes rx hangs) · 7592662d
  Tomasz Wlostowski authored Aug 30, 2012
```
Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
```
  7592662d
28 Aug, 2012 2 commits
- Merge branch 'master' of ohwr.org:hdl-core-lib/wr-cores · d8a50d8c
  Grzegorz Daniluk authored Aug 28, 2012
  
  d8a50d8c
- modules/wr_mini_nic: bugfixes to prevent WRPC from hanging on ping flood · 215b7837
  Grzegorz Daniluk authored Aug 28, 2012
  
  215b7837
13 Aug, 2012 4 commits
- sim/softpll_regs_ng.vh: synced with latest VHDL · 2b913606
  Tomasz Wlostowski authored Aug 13, 2012
  
  2b913606
- sim/simdrv_defs.svh: added set_default_xfer_size() method · b06b345b
  Tomasz Wlostowski authored Aug 13, 2012
  
  b06b345b
- sim/simdrv_minic: driver for latest HDL · 3a1fd6c1
  Tomasz Wlostowski authored Aug 13, 2012
  
  3a1fd6c1
- platform/xilinx/wr_gtp_phy_spartan6: added generic for enabling/disabling GTP… · 5d5baa82
  Tomasz Wlostowski authored Aug 13, 2012
```
platform/xilinx/wr_gtp_phy_spartan6: added generic for enabling/disabling GTP channels (saves logic/BUFG resources on unused channels)
```
  5d5baa82
09 Aug, 2012 2 commits
- pps_gen: separate 1-pps output to drive DIO led · 6a20635e
  Grzegorz Daniluk authored Aug 09, 2012
  
  6a20635e
- tricks and constraints so that the deltaTx/Rx calibration is not necessary for… · 44f102fa
  Grzegorz Daniluk authored Aug 09, 2012
```
tricks and constraints so that the deltaTx/Rx calibration is not necessary for every synthesized WRPC bitstream
```
  44f102fa
06 Aug, 2012 1 commit
- spec_top: turn on vuart in wrpc · 44ca0443
  Grzegorz Daniluk authored Aug 06, 2012
  
  44ca0443
03 Aug, 2012 1 commit

Backport the scu2 design to the pexaria · cd9960f3

Wesley W. Terpstra authored Aug 03, 2012

Add uart over logic analyzer port to exploder and pexaria
Fixup PCIe reference clock SDC (100MHz)

cd9960f3

02 Aug, 2012 4 commits
- wrc_syscon: updated wb slave interface with latest wbgen · 4fd10123
  Grzegorz Daniluk authored Aug 02, 2012
  
  4fd10123
- wr_mini_nic: updated wb slave interface with latest wbgen · ebf189f5
  Grzegorz Daniluk authored Aug 02, 2012
  
  ebf189f5
- Clean up the reset logic for the GSI top files · 8101abab
  Wesley W. Terpstra authored Aug 02, 2012
```
Remove the DDR3 testbench.
```
  8101abab
- removed old softpll core · 2fc4de68
  Grzegorz Daniluk authored Aug 02, 2012
  
  2fc4de68
31 Jul, 2012 3 commits
- spec_top: modelsim does not like or-ing signals inside component · 34c5684c
  Grzegorz Daniluk authored Jul 31, 2012
  
  34c5684c
- define platform dependent stuff only in syn/* Manifest · cad76f7c
  Grzegorz Daniluk authored Jul 30, 2012
  
  cad76f7c
- wr_endpoint/wrc_core: moved t_txtsu_timestamp to endpoint's package · 55c70116
  Tomasz Wlostowski authored Jul 31, 2012
  
  55c70116
26 Jul, 2012 2 commits
- platform/xilinx/wr_gtx_phy_virtex6: generic parameter for choice between global… · f943eba9
  Tomasz Wlostowski authored Jul 26, 2012
```
platform/xilinx/wr_gtx_phy_virtex6: generic parameter for choice between global and regional clock buffers on RX clock
```
  f943eba9
- wr_endpoint: revert to old RX CRC checking algorithm (suspect for RX errors) · 4aef186b
  Tomasz Wlostowski authored Jul 26, 2012
  
  4aef186b
24 Jul, 2012 2 commits
- wr_softpll_ng: CRR_IN/CRR_OUT registers (counter sync) added · 5947d8b3
  Tomasz Wlostowski authored Jul 24, 2012
  
  5947d8b3
- timing/dmtd_with_deglitcher: added counter syncing across multiple DDMTDs · be6a029d
  Tomasz Wlostowski authored Jul 24, 2012
  
  be6a029d
16 Jul, 2012 3 commits
- wr_pps_gen: use correct clock domain reset signal · bd858e7e
  Tomasz Wlostowski authored Jul 16, 2012
  
  bd858e7e
- wr_mini_nic: partially fixed hang-on-RX-flood bug · d16c342d
  Tomasz Wlostowski authored Jul 16, 2012
  
  d16c342d
- modules/wr_endpoint: Tx timestamp strobe generation fixed · b0658a59
  Tomasz Wlostowski authored Jul 12, 2012
  
  b0658a59
12 Jul, 2012 3 commits
- wbp_mux: signals naming cleaned up · 093909a6
  Grzegorz Daniluk authored Jul 12, 2012
  
  093909a6
- Exploder now works too. Wow that was easy to port. · 3122969d
  Wesley W. Terpstra authored Jul 12, 2012
  
  3122969d
- Remove unused signals from SCU top files. · 4c048724
  Wesley W. Terpstra authored Jul 12, 2012
```
Synchronize the SDC file
```
  4c048724
11 Jul, 2012 5 commits
- Fix timing for SCU2 (except DDR) · 28da1529
  Wesley W. Terpstra authored Jul 11, 2012
  
  28da1529
- Remove missing files from the SCU2 project · 08abb2d3
  Wesley W. Terpstra authored Jul 11, 2012
  
  08abb2d3
- Update SCU2 project to use Etherbone package. · 3dc32d81
  Wesley W. Terpstra authored Jul 11, 2012
  
  3dc32d81
- Tom suggested this might be causing packet loss. It was! · f7819ccb
  Wesley W. Terpstra authored Jul 11, 2012
  
  f7819ccb
- fixed wr aux clks, added new files to qsf · 038f7656
  Stefan Rauch authored Jul 11, 2012
```
changed etherbone instantiation
```
  038f7656
10 Jul, 2012 3 commits
- Fix Etherbone in SPEC! · e70ae0bb
  Wesley W. Terpstra authored Jul 10, 2012
  
  e70ae0bb
- Bump LM32 memory to 90KB => improves timings · 66bf1cc9
  Wesley W. Terpstra authored Jul 10, 2012
  
  66bf1cc9
- Included Etherbone into SPEC top design. · caf9d67e
  Wesley W. Terpstra authored Jul 09, 2012
```
However, timing constraints start failing.
```
  caf9d67e