Re-aligment was performed using the WR-enabled FMC-ADC and the PPS signal coming out from the WR
switch as signal input on channel #1, as well as external trigger input. The PPS signal was
delivered to the FMC-ADC by means of a 40ns coaxial cable.

External, internal and time triggering well all tested and calibrated using the above setup.

The new scheme (2x BUFIO2) is causing some routing troubles on the SVEC when WR is also present, so
we provide a generic that allows to use the previous clocking scheme as well.

This is done in order to:

a) Stop using an extra PLL for the ADC serdes and follow the clocking scheme proposed in UG382, v1.10, page 32, Figure 1-15.

b) Decouple the LTC2174-specific code, as a first step to a more generalized acquisition core.

c) Not distribute coregen-generated sources.

Also generate the doc.

Also remove timetag_core component.

syn/svec: split timing constraints for sync_ffs and sync_reg to solve potential issue with sync_reg input bits arriving on different clock cycles

 - Remove duplicate code and introduce a "for loop" generate for the two mezzanines.
 - Complete rework of timing constraints
 - Use SVEC BSP from WR for PLLs and reset
 - Replace xwb_clock_crossing with new xwb_clock_bridge
 - Redefine front panel LED functions, eliminate "heart-beat" LED
 - Fix bug where tm_time_valid was not re-synchronised

 - switch to pipelined
 - replace xwb_register_link with new xwb_register
 - enable pipelined mode for SDB ROM