- 20 May, 2019 5 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
The new scheme (2x BUFIO2) is causing some routing troubles on the SVEC when WR is also present, so we provide a generic that allows to use the previous clocking scheme as well.
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- 06 May, 2019 2 commits
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Dimitris Lampridis authored
This is done in order to: a) Stop using an extra PLL for the ADC serdes and follow the clocking scheme proposed in UG382, v1.10, page 32, Figure 1-15. b) Decouple the LTC2174-specific code, as a first step to a more generalized acquisition core. c) Not distribute coregen-generated sources.
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Dimitris Lampridis authored
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- 03 May, 2019 1 commit
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Dimitris Lampridis authored
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- 02 May, 2019 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 30 Apr, 2019 1 commit
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Dimitris Lampridis authored
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- 21 Mar, 2019 1 commit
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Dimitris Lampridis authored
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- 01 Feb, 2019 1 commit
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Dimitris Lampridis authored
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- 17 Jan, 2019 12 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Tristan Gingold authored
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Tristan Gingold authored
Also generate the doc.
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Tristan Gingold authored
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Tristan Gingold authored
Also remove timetag_core component.
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
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- 03 Dec, 2018 1 commit
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Dimitris Lampridis authored
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- 29 Nov, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 27 Nov, 2018 7 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
syn/svec: split timing constraints for sync_ffs and sync_reg to solve potential issue with sync_reg input bits arriving on different clock cycles
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
- Remove duplicate code and introduce a "for loop" generate for the two mezzanines. - Complete rework of timing constraints - Use SVEC BSP from WR for PLLs and reset - Replace xwb_clock_crossing with new xwb_clock_bridge - Redefine front panel LED functions, eliminate "heart-beat" LED - Fix bug where tm_time_valid was not re-synchronised
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Dimitris Lampridis authored
- switch to pipelined - replace xwb_register_link with new xwb_register - enable pipelined mode for SDB ROM
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- 21 Nov, 2018 1 commit
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Dimitris Lampridis authored
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- 14 Nov, 2018 1 commit
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Dimitris Lampridis authored
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- 07 Nov, 2018 1 commit
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Dimitris Lampridis authored
Adjust tb See merge request dlamprid/fmc-adc-100m14b4cha-gw!1
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- 06 Nov, 2018 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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