- 06 Jul, 2012 2 commits
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Tomasz Wlostowski authored
wr_endpoint: re-generated WB slave, replaced VLAN/PFilter registers by RW/RW types which get synthesized away when not used
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Tomasz Wlostowski authored
wr_endpoint/ep_clock_alignment_fifo: use HW-generated almost_empty flag instead of comparison of word counter with pass_threshold (less resources)
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- 26 Jun, 2012 1 commit
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Tomasz Wlostowski authored
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- 05 Jun, 2012 1 commit
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Grzegorz Daniluk authored
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- 31 May, 2012 1 commit
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Grzegorz Daniluk authored
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- 23 May, 2012 1 commit
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Grzegorz Daniluk authored
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- 22 May, 2012 1 commit
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Grzegorz Daniluk authored
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- 14 May, 2012 10 commits
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Wesley W. Terpstra authored
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Wesley W. Terpstra authored
The problem was that the WR core did not expose the err and rty lines. If a device ever used these lines (the crossbar does for example), then the master would get hung waiting for an answer.
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Stefan Rauch authored
changed WR SFP to SFP2
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Stefan Rauch authored
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Stefan Rauch authored
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Stefan Rauch authored
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Stefan Rauch authored
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Wesley W. Terpstra authored
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Stefan Rauch authored
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Stefan Rauch authored
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- 02 May, 2012 4 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 30 Apr, 2012 3 commits
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 27 Apr, 2012 1 commit
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Grzegorz Daniluk authored
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- 26 Apr, 2012 2 commits
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Tomasz Wlostowski authored
wr_core: wired clk_aux clock (1 channel), default values for inputs, added tm_link_up_o output and wired aux DAC signals
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Tomasz Wlostowski authored
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- 24 Apr, 2012 4 commits
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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- 23 Apr, 2012 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 20 Apr, 2012 5 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 19 Apr, 2012 1 commit
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Tomasz Wlostowski authored
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- 16 Apr, 2012 1 commit
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Tomasz Wlostowski authored
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