modify spll_aligner.vhd
    update lm32 bram file.

    add LM32 ram file for dualport functionality.

    Add extra MINIC/Endpoint in WRPC.
    Add a simple dualport switch module.

    Add a new I2C interface in wrc_syscon for SFP1.

            The bug is introduced by the sentence "wb_out.adr(4 downto 0)=x"02"",
            which should be wb_out.adr(4 downto 0)=b"00010".

The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL
(CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a
BUFG (O) when using ENABLE_SYNC (FALSE)."

I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but
the 10MHz output is still missing. So I have to change the setting of
"cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from
CLKOUT2.

    change the function of LEDs:
      the front end LEDs display the status of link and sync.
      the on-board LEDS display the act of link and PPS.

    Solve compile bug in ucf file.

This reverts commit 21c67bc8.
DCM is much more jittery than PLL_BASE:
DCM_SP:
125MHz -> 62.5MHz: pk-to-pk jitter: 300ps
125MHz -> 125MHz: pk-to-pk jitter: 200ps
20MHz -> 62.5MHz: pk-to-pk jitter: 1772ps (!!!!)

PLL_BASE:
125MHz -> 62.5MHz: pk-to-pk jitter: 185ps
125MHz-> 125MHz: pk-to-pk jitter 161ps
20MHz -> 62.5MHz: pk-to-pk jitter 417ps

syn: remove Makefiles, they are auto-generated and contain paths that are not exportable to other users (such as the location of the Xilinx ISE tools)

This allows to use the same top level vhd for different synthesis targets. Example, we can use the
spec_ref_design from top/ in two different syn/, one for a SPEC45T and another one for a SPEC150T.

hdl: bump general-cores, vme64x-core and gn4124-core to latest version in preparation for updating the SPEC and SVEC reference designs

Every clock management block in Spartan-6 has 2xDCM and 1xPLL. PLLs are therefore a scarcer resource
and should be preserved for user applications whenever possible. In this case, it is very much possible
to generate the necessary clocks via DCMs. Furthermore, we expose the unused CLKFX output of one of the
DCMs (along with a generic to configure the multiplication/division factors), in case it can be used
by the user application.

This guarantees that the 125MHz ref clock and the 62.5MHz system clock will be phase aligned.

(This only affects g_fpga_family = spartan6, when g_use_default_plls = true)