In order to test the jitter noise we changed these constraints. However, a further testing using this constraints should be done to maybe improve the jitter noise

Due to the lack of resources, we cannot use a regional buffer to distribute the 62.5 MHz clock signal. For this reason we use a regional BUFR to divide a global 125 MHz clock and move the divided signal to a BUFG. This ensures that we have this signal available without using additional resources. 

Apart from that we corrected the locked signal path from the rt_subsystem to the top_synthesis file.

Also corrected some indentation. 

As we do not use the Low Jitter Daughterboard but a custom made SCB, the pinout had to be changed for the LJ signals and I2C communication. Also, for coherence, we changed all names refering to LJD and eliminated unnecesary signals, inputs and outputs.

Changed Manifest.py configuration in order to run with older hdl-make and run make synthesis for the first time

Changed general cores and wr cores path to target the specific commit in the OHWR 

Possible through the combination of global and regional clocks. Cannot
have it for all ports because we don't have enough global/regional clock
nets in virtex-6.

Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...

top/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcore

Less code duplication in scb_8ports and scb_18ports top hdl.