is at address 0. This way both CERN and GSI designs have devices located
at the same addresses on the PCI express bus.

When running "hdlmake; make" in a clean project tree, the chipscope ngc files cause the build to fail.

Conflicts:
	modules/wr_endpoint/ep_clock_alignment_fifo.vhd

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

Signed-off-by: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>

platform/xilinx/wr_gtp_phy_spartan6: added generic for enabling/disabling GTP channels (saves logic/BUFG resources on unused channels)

tricks and constraints so that the deltaTx/Rx calibration is not necessary for every synthesized WRPC bitstream

Add uart over logic analyzer port to exploder and pexaria
Fixup PCIe reference clock SDC (100MHz)

Remove the DDR3 testbench.

platform/xilinx/wr_gtx_phy_virtex6: generic parameter for choice between global and regional clock buffers on RX clock