1. 09 Aug, 2019 1 commit
  2. 22 Jan, 2019 3 commits
  3. 21 Jan, 2019 20 commits
  4. 03 Dec, 2018 8 commits
  5. 20 Nov, 2018 1 commit
  6. 16 Nov, 2018 4 commits
  7. 15 Nov, 2018 2 commits
  8. 29 Oct, 2018 1 commit
    • Dimitris Lampridis's avatar
      hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing (re-done) · b6dfc740
      Dimitris Lampridis authored
      Second attempt to use dual reset async fifos and pulse synchronizers. The first one was 9810ef9a,
      later on reverted by 93d49e1f, because it was causing sync problems when unplugging/replugging the
      The problem was in the endpoint's rx path, where one side of the reset (the rx_clk side) was taking
      into account the state of the PHY (via the phy_rdy_i signal), while the other side (the sys_clk
      side) was not. This has been fixed in this commit, by using phy_rdy_i as an active-low reset source
      for both clock domains of the rx path.
      Tested on an SPEC, works.