- 29 Nov, 2023 1 commit
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li hongming authored
change g_reverse_dmtds from true to false
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- 01 Jul, 2020 1 commit
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li hongming authored
1. add pll_status_i clock period constraints 2. correct the TNM_NET name of rx_rec_clk_bufin.
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- 15 May, 2020 1 commit
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li hongming authored
rather than differential signal for 10M input.
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- 14 May, 2020 1 commit
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li hongming authored
There are three types of wrs: normal wrs(mark as wrs), wrs with LJD (mark as WRS-LJD), wrs with embedded lowjitter circuits(mark as WRSLJ). lj_loopback_i/o is used to distinguish wrs from WRS-LJD and WRSLJ. lj_osc_freq_i is used to distinguish WRSLJ from WRS-LJD. lj_osc_freq_i=111 means WRSLJ. lj_osc_freq_i=others means WRS-LJD. lj_osc_freq_i[2 downto 0] need to be pulled up.
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- 06 Apr, 2020 1 commit
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Grzegorz Daniluk authored
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- 03 Apr, 2020 1 commit
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Grzegorz Daniluk authored
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- 20 Jan, 2020 1 commit
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Grzegorz Daniluk authored
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- 07 Jan, 2020 1 commit
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Grzegorz Daniluk authored
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- 17 Dec, 2019 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 09 Dec, 2019 1 commit
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Grzegorz Daniluk authored
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- 30 Aug, 2019 13 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Possible through the combination of global and regional clocks. Cannot have it for all ports because we don't have enough global/regional clock nets in virtex-6.
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
top/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcore
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Tomasz Wlostowski authored
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- 20 Aug, 2019 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 19 Aug, 2019 1 commit
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Grzegorz Daniluk authored
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- 15 Aug, 2019 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Less code duplication in scb_8ports and scb_18ports top hdl.
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- 14 Aug, 2019 1 commit
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Grzegorz Daniluk authored
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- 13 Aug, 2019 1 commit
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Grzegorz Daniluk authored
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- 12 Aug, 2019 1 commit
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Grzegorz Daniluk authored
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- 09 Aug, 2019 8 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Mattia Rizzi authored
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Mattia Rizzi authored
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Mattia Rizzi authored
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Mattia Rizzi authored
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