- 17 Jun, 2013 1 commit
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Lucas Russo authored
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- 07 Jun, 2013 1 commit
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Lucas Russo authored
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- 03 Jun, 2013 1 commit
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Lucas Russo authored
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- 16 Apr, 2013 6 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 11 Apr, 2013 1 commit
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Lucas Russo authored
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- 07 Apr, 2013 1 commit
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Lucas Russo authored
Also, only generic fifos from general-cores are used. No more coregen stuff here
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- 28 Mar, 2013 4 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 21 Mar, 2013 1 commit
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Lucas Russo authored
Now we specify which adc clock will serve as a reference for all adc data paths
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- 19 Mar, 2013 22 commits
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Lucas Russo authored
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Lucas Russo authored
In this way, we can transmit the raw adc data through all FPGA logic, safely. Be aware though, that one must be careful with this simple "trick". If the driving clocks are too different, in frequency, from one another we could have some inconsistencies. This, however, should not be the case as, by default, we work with the same clocks for all channels (chains).
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
The xwb_spi interface was changed and will be referenced in the next commit (update submodule)
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
data/clock delays are now synchronous to sys_clk
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 18 Mar, 2013 2 commits
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Lucas Russo authored
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Lucas Russo authored
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