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spi_master_core: s_STATUS.spi_fsm_clk modified to properly generate the flag for reading the miso buffer.

Testing of reads in m25p32. To work on spi_master_core for generating one-clock signaling for refreshing of received data.

Quick tests in m25p32. All the writing operations simulates properly.

Modifications placed into SPI to allow better compatibility and easy of use while used together with m25p32 controller. Improvements:
- SPI0 initiliazation modified to avoid undesired SPI transactions.
- SPI1 one-clock instructions can trigger now SPI transactions.
- Added waveforms to spi tb

- Syntehsizable @ 125MHz
- All modes of operation implemented.
- Support writes and reads.
- Three independent write fields with selectable length.
- Selectable-length read field.
- Protection against concurrent calls to the internal registers and bad configuration by an user.
- Programmble hold and setup times to adapt to different SPI slave devices.
- Prescaling works nicely.