Updated image1: crossbar added. I2C module, multiboot, m25p32 integrated with basic_trigger. Tests on the way.

i2c documentation up-to-date. Added .gitignore in the i2c_slave_wb_master folder. Everything is correctly synched in this folder.

m25p32 fsm small modifications to look like Xilinx examples: added some extra NOOPs and butterfly reassignment between s_icap_tmp and s_icap_i

Simulation shows that the fsms are correctly working. The fsms work accordingly ug380 but a whole  reconfiguration through simulation is not feasible due to limitations of ICAP simulation. Added Xilinx's examples for multiboot that, truth to be said, are misleading incomplete for a whole multiboot process (not able to customly rewrite the multiboot and golden bitstream addresses).

Committed last modification on IP cores for remote programming before merging: ctdah_lib, i2c_slave_wb_master, m25p32, multiboot, spi_master_multifield

multiboot completely revamped. Synthesizable is achieved but a lot of bugs. Still needs to be simulated.

Added basic_trigger (synchr @200MHz) ready for basic repetition. A combinatorial module with low repetition jitter (basic_trigger_async) is added to the repo, as well.

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spi_master_core: s_STATUS.spi_fsm_clk modified to properly generate the flag for reading the miso buffer.