Commits · 3cc77ba736159ffb0c9dcc8d6c592aab5699c6bb · Projects / White Rabbit Switch - Gateware · Open Hardware Repository

09 Dec, 2019 1 commit
- lpd: update wr-cores for chicken-bits and rx synchronizer · 3cc77ba7
  Grzegorz Daniluk authored Dec 09, 2019
  
  3cc77ba7
30 Aug, 2019 13 commits
- Merge branch 'greg-lpd-rebased' into proposed_master · 5d5f1a74
  Grzegorz Daniluk authored Aug 30, 2019
  
  5d5f1a74
- fix low-jitter constraints after rebase · 868072d9
  Grzegorz Daniluk authored Aug 30, 2019
  
  868072d9
- low phase drift calibration: cleanup 8-port version · 8c21725c
  Grzegorz Daniluk authored Jul 14, 2019
  
  8c21725c
- cleanup low phase drift calibration interface · fe0ba167
  Grzegorz Daniluk authored Jul 12, 2019
  
  fe0ba167
- rt_subsystem: add external samplers for port that are not calibrated for low phase drift · 095c800f
  Grzegorz Daniluk authored Jul 10, 2019
  
  095c800f
- low phase drift calibration only for 12 ports · 1b4724a5
  Grzegorz Daniluk authored Jul 10, 2019
```
Possible through the combination of global and regional clocks. Cannot
have it for all ports because we don't have enough global/regional clock
nets in virtex-6.
```
  1b4724a5
- top: manual control of TX/RX clock buffers for PHYs through generics · 640c7bb4
  Tomasz Wlostowski authored Jul 03, 2019
  
  640c7bb4
- constraining tx_out clock produced by GTX_LP · 0f99e5cf
  Grzegorz Daniluk authored Jun 19, 2019
  
  0f99e5cf
- phy determinism for 18-port version · d49e5993
  Grzegorz Daniluk authored Jun 19, 2019
  
  d49e5993
- Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of… · 5eb9d456
  Tomasz Wlostowski authored Nov 14, 2018
```
Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...
```
  5eb9d456
- top/scb_8ports: 8-port PoC firmware with deterministic V6 transceiver config · bbe909f5
  Tomasz Wlostowski authored Jun 19, 2018
  
  bbe909f5
- top/bare_top: move DDMTD samplers to the PHY module, g_without_network… · 93a74f10
  Tomasz Wlostowski authored Jun 19, 2018
```
top/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcore
```
  93a74f10
- wrsw_rt_subsystem: allow externally sampled RX clocks (DDMTD inside the PHY module) · 6b3c0e71
  Tomasz Wlostowski authored Jun 19, 2018
  
  6b3c0e71
20 Aug, 2019 2 commits
- update wr-cores: low-jitter support merged to proposed_master · 205a4500
  Grzegorz Daniluk authored Aug 20, 2019
  
  205a4500
- Merge branch 'greg-low-jitter' into proposed_master · ebe9d4c9
  Grzegorz Daniluk authored Aug 20, 2019
  
  ebe9d4c9
19 Aug, 2019 1 commit
- ljd: use ad9516 lock signal and reset it with ext_pll_reset bit · 76eaac7d
  Grzegorz Daniluk authored Aug 19, 2019
  
  76eaac7d
15 Aug, 2019 2 commits
- add _ljd_ prefix to everything Low-Jitter Daughterboard related · 90536db3
  Grzegorz Daniluk authored Aug 15, 2019
  
  90536db3
- ljd: move daughterboard detection inside rt subsystem · f8127017
  Grzegorz Daniluk authored Aug 15, 2019
```
Less code duplication in scb_8ports and scb_18ports top hdl.
```
  f8127017
14 Aug, 2019 1 commit
- wrs_ljd: use bufr for 8port like to 18port · 0e2e8d7c
  Grzegorz Daniluk authored Aug 14, 2019
  
  0e2e8d7c
13 Aug, 2019 1 commit
- softpll: use generic to define number of ext channels · 8d17a35c
  Grzegorz Daniluk authored Aug 13, 2019
  
  8d17a35c
12 Aug, 2019 1 commit
- rename ext_board_check to wrsw_ext_board_check · 1a8c42fa
  Grzegorz Daniluk authored Aug 12, 2019
  
  1a8c42fa
09 Aug, 2019 11 commits
- remove unused I/Os and assign default values · 5e7d55d6
  Grzegorz Daniluk authored Aug 09, 2019
  
  5e7d55d6
- wrsw_ext_board: synchronous reset for FSM · 1c33a80f
  Grzegorz Daniluk authored Aug 09, 2019
  
  1c33a80f
- wrsw_ext_board: fix formatting, no technical change · 78d3f242
  Grzegorz Daniluk authored Aug 09, 2019
  
  78d3f242
- rt_subsystem: add generic for low jitter daughterboard support · a8d8867f
  Grzegorz Daniluk authored Aug 08, 2019
  
  a8d8867f
- Modified synthesis configuration for 18ports build · b5489272
  Mattia Rizzi authored Dec 20, 2016
  
  b5489272
- Modified constraints for low-jitter daughterboard · 7d9971a2
  Mattia Rizzi authored Aug 09, 2019
  
  7d9971a2
- Updated wr-cores for external board · 31d7252e
  Mattia Rizzi authored Dec 20, 2016
  
  31d7252e
- Modifed Manifests to build correctly the project file · fb524f59
  Mattia Rizzi authored Dec 20, 2016
  
  fb524f59
- Added support for the external board · 0b1aba5a
  Mattia Rizzi authored Dec 20, 2016
  
  0b1aba5a
- Added a powerdown line to shutdown the noisy MMCMs when external PLL is detected · 85dd1047
  Mattia Rizzi authored Dec 20, 2016
  
  85dd1047
- Added module to check the presence of the external board · 98089675
  Mattia Rizzi authored Dec 20, 2016
  
  98089675
05 Jun, 2019 1 commit
- add bit to control WRS 1-PPS in termination · 31787035
  Grzegorz Daniluk authored Sep 13, 2018
  
  31787035
13 May, 2019 1 commit
- Merge branch 'greg-mirroring' into proposed_master · 246f32a1
  Grzegorz Daniluk authored May 13, 2019
  
  246f32a1
10 May, 2019 2 commits
- add port mirroring for NIC/CPU originated traffic · 6935e96c
  Grzegorz Daniluk authored May 10, 2019
  
  6935e96c
- pass NIC originated RTU decisions through RTU module · b01a8ee9
  Grzegorz Daniluk authored May 10, 2019
  
  b01a8ee9
09 May, 2019 3 commits
- fix simulation for modern Modelsim versions · ac150620
  Grzegorz Daniluk authored May 09, 2019
  
  ac150620
- fix simulation after reset changes in wr-cores · 3073df19
  Grzegorz Daniluk authored May 09, 2019
  
  3073df19
- update wr-cores to fix simulation after nic and txtsu move · aa7aca2a
  Grzegorz Daniluk authored May 09, 2019
  
  aa7aca2a