- 18 Jun, 2014 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 17 Jun, 2014 2 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 09 Apr, 2014 1 commit
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Grzegorz Daniluk authored
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- 20 Mar, 2014 1 commit
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Grzegorz Daniluk authored
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- 18 Mar, 2014 1 commit
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Grzegorz Daniluk authored
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- 14 Mar, 2014 2 commits
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Grzegorz Daniluk authored
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Maciej Lipinski authored
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- 20 Feb, 2014 4 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 19 Feb, 2014 2 commits
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Maciej Lipinski authored
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Tomasz Wlostowski authored
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- 18 Feb, 2014 4 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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- 17 Feb, 2014 6 commits
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Maciej Lipinski authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 14 Feb, 2014 1 commit
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Grzegorz Daniluk authored
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- 06 Feb, 2014 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 05 Feb, 2014 5 commits
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Grzegorz Daniluk authored
HWIU provides more information about the gateware build and in the same time can read debug registers and drive chipscope mux in the same way HWDU does it. For now one of them can be selected with generic, but once I test HWIU I'll remove HWDU module.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
Conflicts: Manifest.py ip_cores/general-cores modules/wrsw_nic/nic_tx_fsm.vhd modules/wrsw_nic/nic_wbgen2_pkg.vhd modules/wrsw_nic/nic_wishbone_slave.vhd modules/wrsw_nic/wrsw_nic.vhd modules/wrsw_nic/xwrsw_nic.vhd top/bare_top/scb_top_bare.vhd top/bare_top/wrsw_components_pkg.vhd top/bare_top/wrsw_top_pkg.vhd top/scb_18ports/scb_top_synthesis.vhd
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- 04 Feb, 2014 6 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
- removed declarations of unused signals - reduced padding_size to bits needed for padding possible runt Ethernet frames - simplified signal assignments and conditions in FSM (e.g. no need to check if needs_padding = 1 and padding_size /= 0, because when former is true, the latter is always true too) - moved assignment of outputs validated with other outputs outside FSM to simplify the logic (fake rtu decision)
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Grzegorz Daniluk authored
Instead of old fabtic converted to Pipelined WB using ep_rx_wb_master module from endpoint_private_pkg
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Grzegorz Daniluk authored
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