HWIU provides more information about the gateware build and in the same time can
read debug registers and drive chipscope mux in the same way HWDU does it. For
now one of them can be selected with generic, but once I test HWIU I'll remove
HWDU module.

Conflicts:
	Manifest.py
	ip_cores/general-cores
	modules/wrsw_nic/nic_tx_fsm.vhd
	modules/wrsw_nic/nic_wbgen2_pkg.vhd
	modules/wrsw_nic/nic_wishbone_slave.vhd
	modules/wrsw_nic/wrsw_nic.vhd
	modules/wrsw_nic/xwrsw_nic.vhd
	top/bare_top/scb_top_bare.vhd
	top/bare_top/wrsw_components_pkg.vhd
	top/bare_top/wrsw_top_pkg.vhd
	top/scb_18ports/scb_top_synthesis.vhd

- removed declarations of unused signals
- reduced padding_size to bits needed for padding possible runt Ethernet
  frames
- simplified signal assignments and conditions in FSM (e.g. no need to
  check if needs_padding = 1 and padding_size /= 0, because when former
  is true, the latter is always true too)
- moved assignment of outputs validated with other outputs outside FSM
  to simplify the logic (fake rtu decision)

Instead of old fabtic converted to Pipelined WB using ep_rx_wb_master
module from endpoint_private_pkg

- removed ARB_DISABLED state, instead FSM is hold in ARB_START_SCAN
  unless module is enabled
- removed declarations of unused signals (granted_desc_idx, desc_idx_d0,
  check_count, stupid_hack)
- moved assignment of outputs validated with other signals outside FSM
  to simplify the logic (txdesc_current_o/rxdesc_current_o are validated
  by desc_grant_o, and stored in internal registers of nic_rx_fsm and
  nic_tx_fsm)
- rewritten ARB_WRITE_DESC state, so that data output is driven by
  desc_subreg counter instead of separate counter in case statement.
- more exotic regnums in marshalling functions (nic_descriptors_pkg) to
  minimize logic required to output correct data when needed in modified
  ARB_WRITE_DESC state

Just a cleanup to have all subprobrams the same type (functions) in the
package.

[switch-optimization]: wrsw_nic/nic_elastic_buffer: use native almost_full and almost_empty for generating stall

Xilinx FIFOs have native almost_empty and almost_full outputs driven at
configured thresholds. Using them saves few LUTs comparing to stall
generation based on usedw counter as it was done earlier.

It's just a trivial clean up commit, it does not save any resources.

The values used by WR Switch software fit in 8-bit registers.

[sim/testbench] adding possibility of easily settin many untagged VLANs to EP driver + some usecases to main.vs