1.- Write into m25p32 SR works: we are able to protect SPI memory space.
2.-  Starting to work in the Write Page test. Good synchronization between m25p32 controller, double buffer and SPI. Needs to load some data and check agains the serializer RX.
3.- Extra test: when an access over the SPI interface in being performed, the core doesn't allow to reconfigure the FMOH register, responsible of changing the fsm of the m25p32 controller.

General: big cleanup of the code. Everything is commented. Code size smaller.

Known issues to resolved:
- Implement FMOH bits: CLBR, FS, PG, SECT
- Implement SPI1 CLK_DIV bit
- Implement read operation in SPI module
- Implement CTR1 bits: BOV, CBSF
- Implement Write Page Operation in m25p32

This core starts to get ready.

- Synthesizable. Simulations reveals some little bugs in SPI cs_n pin and no loading of the registers.
- The VHDL syntax uses extensively type record entities, translation functions between IOs and records, attributes for defined type records...
- m25p32_core.vhd has now a package for itself m25p32_core_pkg.vhd. This file contains procedures for all the chain of spi instruction to write and read from the memory through SPI. It needs to add more cases.

It still needs work to do.

- Added documentation in pdf about register and memory map.
- Added testbench of the spi_master_core.

- Creation of a "hdl/ctdah_pkg: which share common components used along the design.
- Creation of m24p32 HDL core for managing access to m25p32 memory.
--- m24p32 is better structured by using packages, records and fucntions for easy translation.
- Creation of "hdl/spi_master_multified" for communicating with m24p32
- Modification "hdl/i2c_slave_wb_master" for better readability.

WR core implementation for CONV-TTL-BLO. Bitstream has been generated. Pending the test of WR upon a set up of a WR link.

Now is easy to understand all the FSMs and easy to debug, whenever it will be needed.
TODO:
- Fix a bug with regards a master wishbone operation at the end of a i2c slave write into sda operation

Possible small incompatibilities of independent HDL cores with its own testbench.
image1 status:
- i2c_slave is correctly initializated
- control is being heavily debugged
- triggers are being configured for proper use after initialization
TODO
- Check trigger initialization
- Complete i2c configuration check
- multiboot core to be checked

- Before read/write bit in ICAP_SPARTAN6 was inverted(solved)
- Missed a few states(dummies and so on) for correcty timing.
- TODO: MODE register should be added in the setting up. First the module should be tested in FPGA.