However, timing constraints start failing.

=> needed for preloaded firmware (ie: production cards)
=> needed to program firmware over JTAG

=> needed for gdb connection
=> needed for loading LM32 firmware over JTAG

wr_endpoint: re-generated WB slave, replaced VLAN/PFilter registers by RW/RW types which get synthesized away when not used

wr_endpoint/ep_clock_alignment_fifo: use HW-generated almost_empty flag instead of comparison of word counter with pass_threshold (less resources)

Forgot to use the xilinx specific package in the spec.

Update the SCU usage of the wrcore (and attached SFP)
Move the pow_reset and flash_loader into altera platform components

  * Added the new SCU2 target (different pinouts and components)
  * Moved common components (uart) to modules
  * Moved the common spec and SCU DAC files into modules
  * Added the DDR3 controller for Altera
  * Removed a few superfluous files from version control

The problem was that the WR core did not expose the err and rty lines.
If a device ever used these lines (the crossbar does for example),
then the master would get hung waiting for an answer.

changed WR SFP to SFP2