- 24 Oct, 2018 12 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
hdl: add bit to clear last trigger status, and prevent trigger status from updating when not in acquisition
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
hdl: removed carrier one-wire master (now handled by WR PTP core), introduced SPI Flash interface for WR PTP core, migrated all carrier HDL to 62.5MHz clock (FMC-ADC and DMA datapath still on 125MHz)
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Dimitris Lampridis authored
hdl: integrated WR PTP core (SPEC only for now), tested, works, need to review calibration procedure
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Dimitris Lampridis authored
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- 31 Jan, 2018 5 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 26 Jan, 2018 2 commits
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Dimitris Lampridis authored
hdl: modify trigger tag data to include metavalue (0xACCE55) and also reorder the trigger tag seconds field to make it more readable
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Dimitris Lampridis authored
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- 25 Jan, 2018 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
The new trigger logic allows for logical OR'ing of all trigger sources, by means of the new "trigger enable" register. For each trigger the "mask" of the trigger source(s) is reflected in the "trigger status" register and it is also stored in the data stream together with the trigger time tag. Furthermore, the previously used glitch filter has been removed, in favor of a comparator module with optional hysteresis. This approach makes the internal trigger logic more responsible, versatile and intuitive to the user. The SPEC testbench has been updated to test these new features. It is still far from perfect though, see also issue #1726.
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- 23 Jan, 2018 1 commit
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Dimitris Lampridis authored
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- 22 Jan, 2018 1 commit
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Tim Mottram authored
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
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- 23 Jun, 2016 6 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
hdl: stop using local ext_pulse_sync, switch to general-cores sync chain for external trigger as well
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- 22 Jun, 2016 3 commits
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Dimitris Lampridis authored
hdl: replace custom ext_pulse_sync with general-cores module for time trigger sync, cleanup timetag_core, tested on SPEC in the lab, works
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 16 Jun, 2016 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 13 Jun, 2016 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 08 Jun, 2016 1 commit
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Dimitris Lampridis authored
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- 19 May, 2016 1 commit
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Dimitris Lampridis authored
Also point to new, stable release of DDR3 core (1.0) which also fixes the reset logic
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- 17 May, 2016 1 commit
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Dimitris Lampridis authored
It is more natural to read a zero value from a register during normal operation / after reset. Also avoids the extra logic outside of the wbgen carrier_csr which was needed to accomodate the non-default value of '1'
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- 13 May, 2016 1 commit
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Dimitris Lampridis authored
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