spi_master_core: s_STATUS.spi_fsm_clk modified to properly generate the flag for reading the miso buffer.

Testing of reads in m25p32. To work on spi_master_core for generating one-clock signaling for refreshing of received data.

Quick tests in m25p32. All the writing operations simulates properly.

Modifications placed into SPI to allow better compatibility and easy of use while used together with m25p32 controller. Improvements:
- SPI0 initiliazation modified to avoid undesired SPI transactions.
- SPI1 one-clock instructions can trigger now SPI transactions.
- Added waveforms to spi tb

- Syntehsizable @ 125MHz
- All modes of operation implemented.
- Support writes and reads.
- Three independent write fields with selectable length.
- Selectable-length read field.
- Protection against concurrent calls to the internal registers and bad configuration by an user.
- Programmble hold and setup times to adapt to different SPI slave devices.
- Prescaling works nicely.

1.- Write into m25p32 SR works: we are able to protect SPI memory space.
2.-  Starting to work in the Write Page test. Good synchronization between m25p32 controller, double buffer and SPI. Needs to load some data and check agains the serializer RX.
3.- Extra test: when an access over the SPI interface in being performed, the core doesn't allow to reconfigure the FMOH register, responsible of changing the fsm of the m25p32 controller.

General: big cleanup of the code. Everything is commented. Code size smaller.

Known issues to resolved:
- Implement FMOH bits: CLBR, FS, PG, SECT
- Implement SPI1 CLK_DIV bit
- Implement read operation in SPI module
- Implement CTR1 bits: BOV, CBSF
- Implement Write Page Operation in m25p32

This core starts to get ready.