- 30 Sep, 2012 1 commit
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gilsoriano authored
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- 27 Sep, 2012 2 commits
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gilsoriano authored
Quick tests in m25p32. All the writing operations simulates properly.
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gilsoriano authored
Modifications placed into SPI to allow better compatibility and easy of use while used together with m25p32 controller. Improvements: - SPI0 initiliazation modified to avoid undesired SPI transactions. - SPI1 one-clock instructions can trigger now SPI transactions. - Added waveforms to spi tb
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- 25 Sep, 2012 4 commits
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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- 21 Sep, 2012 1 commit
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gilsoriano authored
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- 20 Sep, 2012 1 commit
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gilsoriano authored
- Syntehsizable @ 125MHz - All modes of operation implemented. - Support writes and reads. - Three independent write fields with selectable length. - Selectable-length read field. - Protection against concurrent calls to the internal registers and bad configuration by an user. - Programmble hold and setup times to adapt to different SPI slave devices. - Prescaling works nicely.
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- 17 Sep, 2012 1 commit
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gilsoriano authored
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- 14 Sep, 2012 1 commit
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gilsoriano authored
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- 12 Sep, 2012 2 commits
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gilsoriano authored
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gilsoriano authored
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- 22 Aug, 2012 7 commits
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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- 21 Aug, 2012 5 commits
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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gilsoriano authored
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- 08 Aug, 2012 2 commits
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gilsoriano authored
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gilsoriano authored
1.- Write into m25p32 SR works: we are able to protect SPI memory space. 2.- Starting to work in the Write Page test. Good synchronization between m25p32 controller, double buffer and SPI. Needs to load some data and check agains the serializer RX. 3.- Extra test: when an access over the SPI interface in being performed, the core doesn't allow to reconfigure the FMOH register, responsible of changing the fsm of the m25p32 controller. General: big cleanup of the code. Everything is commented. Code size smaller.
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- 06 Aug, 2012 1 commit
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gilsoriano authored
Known issues to resolved: - Implement FMOH bits: CLBR, FS, PG, SECT - Implement SPI1 CLK_DIV bit - Implement read operation in SPI module - Implement CTR1 bits: BOV, CBSF - Implement Write Page Operation in m25p32 This core starts to get ready.
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- 03 Aug, 2012 2 commits
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gilsoriano authored
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gilsoriano authored
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- 02 Aug, 2012 2 commits
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gilsoriano authored
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gilsoriano authored
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- 01 Aug, 2012 1 commit
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gilsoriano authored
- Synthesizable. Simulations reveals some little bugs in SPI cs_n pin and no loading of the registers. - The VHDL syntax uses extensively type record entities, translation functions between IOs and records, attributes for defined type records... - m25p32_core.vhd has now a package for itself m25p32_core_pkg.vhd. This file contains procedures for all the chain of spi instruction to write and read from the memory through SPI. It needs to add more cases. It still needs work to do.
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- 26 Jul, 2012 2 commits
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gilsoriano authored
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gilsoriano authored
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- 24 Jul, 2012 1 commit
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gilsoriano authored
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- 23 Jul, 2012 1 commit
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gilsoriano authored
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- 20 Jul, 2012 1 commit
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gilsoriano authored
- Added documentation in pdf about register and memory map. - Added testbench of the spi_master_core.
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- 27 Jun, 2012 1 commit
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gilsoriano authored
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- 22 Jun, 2012 1 commit
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gilsoriano authored
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