- 23 Apr, 2020 28 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
It is required to delay the start signal (compared to values), as the vtu needs 1 cycle to check the values.
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 21 Apr, 2020 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 02 Apr, 2020 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 01 Apr, 2020 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 31 Mar, 2020 3 commits
- 27 Mar, 2020 1 commit
-
-
John Gill authored
-
- 26 Mar, 2020 1 commit
-
-
Tristan Gingold authored
-
- 25 Mar, 2020 1 commit
-
-
John Gill authored
Fixed some constraints. Some paths not constrained; eg no clocks on tmg_io pins, many CDCs go from fast into slow domains need reviewing to ensure pulse widths can be captured and latched.
-